1. Field of the Invention
The present invention relates to memories implemented in the form of a matrix network of memory cells in an integrated circuit. The present invention more specifically applies to memories provided with a redundancy element for functionally replacing a defective element of the memory (for example, a column or a row).
2. Discussion of the Related Art
The use of a redundancy element to replace a defective element must be performed transparently for the user. Memory circuits are thus generally associated with redundancy or repair circuits, meant to permanently modify the selection of the memory columns when one of these columns has failed a test. For this purpose, fuses operated during a test phase of the manufacturing process are generally used. Several architectures may be used to organize the routing of the decoded column addresses.
A first architecture provides a redundancy column next to a group of columns forming the matrix, and associates each column, that might be replaced, with a fuse to connect, in the place of a defective column, the redundancy column.
A second architecture uses a fuse matrix to store the address of the defective column and a comparator receiving the address of the column and the defective address stored by the fuse matrix. The comparator directs, upon each reading from or writing into the memory, the current datum to the redundancy column if the current address corresponds to the address stored by the fuse matrix.
More recently, redundancy circuits reducing the number of necessary fuses to implement replacement of a defective element of the memory have been provided. Such circuits consist of shifting, from one column and from column to column, the addressing of the memory towards the redundancy column, each column in the memory being capable of being used as a replacement column for the preceding column. The advantage of such circuits with respect to prior solutions is that they make the times of access to the memory cells uniform, even in case of a use of the redundancy column. Examples of redundancy circuits of this type are described in patents WO-A-9406082 and EP-A-0477809 which patents are incorporated herein by reference.
FIG. 1 shows a conventional example of a redundancy memory circuit of the type described in patent WO-A-9406082. This drawing shows a memory circuit including two groups or matrix networks 1, 1′ of memory cells 2, 2′ likely to each store one data bit. Each network 1, 1′ includes m rows and n+1 columns, the n+1-th column forming a redundancy column for replacing a column containing a defective cell among the n first columns. Cells 2, 2′ are addressed by means of an address bus 3 carrying, in the form of a binary address, the coordinates (column and row) of a memory word formed of several bits.
In the example shown, it is assumed that a memory word includes two bits and that each network 1, 1′ is associated with one bit of a memory word. The binary address of a memory word is carried by bus 3 over k bits. This address is decoded by row and column decoders 4 and 5, for extracting from address A carried by bus 3 a row address Ar and a column address Ac, that is, the vertical and horizontal coordinates of the memory word in the memory. Generally, the column address is carried by least significant bits of address A, while the row address is carried by most significant bits. m outputs of decoder 4 form row conductors 6 enabling to select the row of the addressed memory word, a single one of the row conductors being active. Column decoder 5 is meant to activate a column conductor 7 of each group 1, 1′ corresponding to the column address of the memory word.
Each matrix network 1, 1′ is associated with a data input/output 8, 8′ on which the memory word is input or read. Each terminal 8, 8′ is associated with a read amplifier 9, 9′ and with a write amplifier 10, 10′. Each network 1, 1′ is further associated with a multiplexer 11, 11′ for routing the data bit to a column conductor 7, 7′ of network 1, 1′. The selection of conductor 7, 7′ is performed based on column address Ac.
A redundancy circuit 12 is interposed between n outputs of decoder 5 and n+1 control inputs of multiplexers 11, 11′. Circuit 12 is formed by a fuse circuit 13 and a routing circuit 15. Circuits 13 and 15 are, in practice, overlapping and have the function of shifting the electric connection from an output conductor 14 of decoder 5 to a conductor 16 of next rank at the output of circuit 15 if the conductor 16 of same rank as conductor 14 is associated with a column 7 or 7′ including a defective cell 2 or 2′. Thus, circuit 13 includes as many fuses as decoder 5 includes outputs 14 and circuit 15 includes as many output 16 as each of networks 1 and 1′ include columns 7, 7′. If the connection of a conductor 14 is shifted to a conductor 16 of next rank, this shifting is repeated for all conductors 14 of higher rank so that the conductor 14 of highest rank is associated with the redundancy column.
A disadvantage of conventional redundancy architectures is that the shifting, as concerns the addressing, of a defective column to the next column to use the redundancy column is performed simultaneously for all networks 1, 1′ as soon as one of these networks includes a defective cell. Thus, the circuit must include as many redundancy columns as there are matrix networks 1, 1′ associated with a data bit even when only a single defective column in the entire memory can be corrected or repaired by the redundancy columns.
Another disadvantage of conventional circuits equipped with redundancy elements is that they use destructive fusible elements (for example, which can be fused by laser or electric current) or the state of which is modified irreversibly to modify, from the addressing viewpoint, the organization of the columns of the matrix networks. This leads, in practice, to implementing a redundancy element only during tests performed during the memory manufacturing. Indeed, it is generally not desirable to enable an end user to act in a definitive manner upon the internal structure of an integrated circuit. Now, the failure of the memory cell may occur during the operation of a system with which the memory is associated. In such a case, the memory circuit conventionally becomes unusable even when a redundancy element can remain available.